High-speed serial input/output (I/O) interfaces have recently been targeting 8-10 Gbit speeds. Providing reliable data communications at these speeds is often complex and challenging as inter-symbol interference (ISI), random and deterministic jitter, crosstalk and supply noise can severely degrade the signal, which results in challenges to recover the signal on the receiver side. In the PCIe, (Generation 3) specification, for example, an interactive back channel equalization protocol is defined. This protocol allows link partners to exchange information and allocates a time window for each receiver to adjust its link partner's transmitter settings. However, the protocol does not specify a method for the receiver to adapt, but the transmitter side of the link partner must respond to its request.
Current solutions for utilizing link equalization require every platform and add-in card to be characterized and configured individually for reliable operation. This combined with individual platform customization represents a huge logistics challenge for electrical validation.